MCA 217 Advanced Computer Architecture Notes cover all 4 units of the GGSIPU MCA Semester 3 elective in 82 pages, with 24 solved numericals, 37 labelled diagrams and 80 exam-style practice questions. They follow the MCA scheme for batches from academic session 2025-26 onwards and are sold as a printed book.
Written by Prateek Talwar, Founder, Unnati Educations · Reviewed by Ritik Rawat, B.Tech, Senior Full Stack Developer · Checked against the GGSIPU MCA Scheme of Examination and Detailed Syllabus (BoS of USIC&T, 28 July 2025) · Updated 13 October 2026 · Editorial policy
Scheme: MCA (2 years), A.S. 2025-26 onwards | Applies to: batches from academic session 2025-26 onwards | Verified against: MCA Scheme of Examination and Detailed Syllabus, BoS 28/07/2025, AC Sub Committee 01/08/2025
MCA 217 Advanced Computer Architecture at a glance: GGSIPU MCA Sem 3 credits, units and exam pattern
MCA 217 is one of eleven Core Elective II options, chosen instead of papers such as MCA-219 Distributed Systems. It sits with the other GGSIPU MCA Semester 3 papers.
| Code and title | MCA-217 Advanced Computer Architecture |
|---|---|
| Course and semester | MCA (2 years), Semester 3 |
| Category and credits | Core Elective II · 3 credits · L 3, T/P none |
| Marks | Out of 100 (pass mark note in the scheme); end-term 60; internal split not printed in the official PDF |
| End-term pattern | Compulsory Q1 of short answers, 12 marks, plus one of two questions from each unit, 12 marks each (12 + 48 = 60 marks) |
| Applies to | Academic session 2025-26 onwards |
| Units and prerequisite | 4 units of 10 hours each · Computer Organization |
| Paired lab | MCA-265 Lab based on Core Elective II (Advanced Computer Architecture Lab), L 0, T/P 2, 1 credit |
The official PDF numbers the MCA 217 units I to IV but prints no unit titles, so this page uses the titles from the notes.
MCA 217 Advanced Computer Architecture Notes unit-wise: 24 solved numericals and 37 diagrams across 4 units
These MCA 217 Advanced Computer Architecture IPU notes run to 82 pages, and each unit closes with a Quick Revision Sheet, a Common Mistakes box and an Exam Corner. The sample PDF in the header shows one content page per unit. Notes for every other paper sit under GGSIPU MCA notes.
MCA 217 Unit 1: Parallel Computer Models, Program Properties and Interconnection Networks
Unit 1 (pages 3 to 26) builds the performance toolkit: CPU time T = Ic × CPI × τ, MIPS, UMA, NUMA and COMA against NORMA multicomputers, the SIMD 5-tuple, and speedup, efficiency, redundancy, utilisation and quality with Amdahl, Gustafson and Sun-Ni laws. It then covers data dependences, Bernstein's conditions, grain packing, dataflow machines, and static and dynamic networks up to the Omega network and combining. It has 11 sections, 8 solved examples, 11 figures and 20 practice questions.
| Network | Degree | Diameter | Links |
|---|---|---|---|
| Ring | 2 | ⌊N/2⌋ | N |
| 2D mesh (r × r) | 4 | 2(r − 1) | 2N − 2r |
| Binary n-cube | n | n | nN/2 |
| Completely connected | N − 1 | 1 | N(N − 1)/2 |
Quick look: static network parameters for N nodes (from page 21)
- Network
- Ring
- Degree
- 2
- Diameter
- ⌊N/2⌋
- Links
- N
- Network
- 2D mesh (r × r)
- Degree
- 4
- Diameter
- 2(r − 1)
- Links
- 2N − 2r
- Network
- Binary n-cube
- Degree
- n
- Diameter
- n
- Links
- nN/2
- Network
- Completely connected
- Degree
- N − 1
- Diameter
- 1
- Links
- N(N − 1)/2
MCA 217 Unit 2: Processors, SIMD and Vector Architectures and Memory Hierarchy
Unit 2 (pages 27 to 45) covers SPARC register windows, the degree-m superscalar speedup, VLIW against superscalar issue, the SIMD design space with CM-2 and MasPar MP-1, vector chaining on the Cray-1, and systolic arrays. The memory half teaches inclusion, coherence and locality, effective access time and cost of a three-level hierarchy, low-order and high-order interleaving, pipelined access θ + (m − 1)τ, and physical against virtual address caches. It has 10 sections, 8 solved examples, 10 figures and 20 practice questions.
Quick look: where does address 29 go in an 8-module memory? (from page 41)
- 128 words in 8 modules of 16 words: 3 module bits, 4 word bits, so 29 = 0011101.
- Low-order: last 3 bits (101) pick module M5, word 3. Check: 29 mod 8 = 5.
- High-order: first 3 bits (001) pick module M1, word 13. Check: 29 div 16 = 1.
MCA 217 Unit 3: Pipelining and Superscalar Techniques
Unit 3 (pages 46 to 64) is the formula-heavy unit. It sets the clock period τ = max(τi) + d, derives speedup, efficiency and throughput of a k-stage pipeline, and takes a nonlinear reservation table through forbidden latencies, collision vector, state diagram and MAL. It also covers prefetch buffers and internal forwarding, scoreboarding against Tomasulo, delayed branches, 2-bit predictors and the BTB, the floating-point adder, Wallace-tree multiplier, TI-ASC, and superpipelined superscalar design. It has 8 sections, 5 solved examples, 10 figures and 20 practice questions.
Quick look: cost of taken branches in a 500 MHz pipeline (from page 57)
p = 0.2, q = 0.6, b = 3 → pqb = 0.36
CPIeff = 1 + pqb = 1.36
Heff = 500 / 1.36 = 367.6 MIPS
D = 0.36 / 1.36 = 26.5%About a quarter of the throughput goes to taken branches.
MCA 217 Unit 4: Multithreading, MIMD Architectures, Cache Coherence and Parallel Programming
Unit 4 (pages 65 to 82) derives multithreaded processor efficiency from N, R, L and C, compares coarse-grained, fine-grained and simultaneous multithreading, and covers latency hiding and MIMD design. It then teaches Test&Set, Fetch&Add and LL/SC, four consistency models, snoopy MSI and MESI, full-map and limited directories, the five parallel programming models and parallelising compiler phases. It has 8 sections, 3 solved examples, 6 figures and 20 practice questions.
| State | Memory up to date? | Write without a bus transaction? |
|---|---|---|
| M (Modified) | No | Yes |
| E (Exclusive) | Yes | Yes, moves to M |
| S (Shared) | Yes | No, invalidate others first |
| I (Invalid) | Not valid | Not applicable |
Quick look: MESI cache-block states (from page 74)
- State
- M (Modified)
- Memory up to date?
- No
- Write without a bus transaction?
- Yes
- State
- E (Exclusive)
- Memory up to date?
- Yes
- Write without a bus transaction?
- Yes, moves to M
- State
- S (Shared)
- Memory up to date?
- Yes
- Write without a bus transaction?
- No, invalidate others first
- State
- I (Invalid)
- Memory up to date?
- Not valid
- Write without a bus transaction?
- Not applicable
MCA 217 exam corner: 40 short-answer and 40 long-answer practice questions by unit
Each unit ends with 10 short-answer questions for Q1 and 10 long-answer questions for the 12-mark unit questions. They are practice sets without printed answers.
| Unit | Short-answer | Long-answer | Solved numericals |
|---|---|---|---|
| Unit 1 | 10 | 10 | 8 |
| Unit 2 | 10 | 10 | 8 |
| Unit 3 | 10 | 10 | 5 |
| Unit 4 | 10 | 10 | 3 |
| Total | 40 | 40 | 24 |
MCA 217 practice questions and solved numericals per unit
- Unit
- Unit 1
- Short-answer
- 10
- Long-answer
- 10
- Solved numericals
- 8
- Unit
- Unit 2
- Short-answer
- 10
- Long-answer
- 10
- Solved numericals
- 8
- Unit
- Unit 3
- Short-answer
- 10
- Long-answer
- 10
- Solved numericals
- 5
- Unit
- Unit 4
- Short-answer
- 10
- Long-answer
- 10
- Solved numericals
- 3
- Unit
- Total
- Short-answer
- 40
- Long-answer
- 40
- Solved numericals
- 24
The MCA 217 notes give 40 short-answer and 40 long-answer practice questions across 4 units, plus 24 solved numericals.
One question per unit, with answer pointers:
- Unit 1: What is the maximum speedup if 10% of the code is sequential? Pointer: α is the sequential fraction, so S(∞) = 1/α = 10.
- Unit 2: What is vector chaining? What is strip mining? Pointer: chaining feeds one vector pipeline's result into the next; strip mining splits a long vector into 64-element strips.
- Unit 3: Compare Tomasulo's algorithm with scoreboarding. Pointer: reservation stations, tags and the Common Data Bus rename registers, so WAR and WAW vanish.
- Unit 4: Define sequential and weak consistency. Pointer: one global order of all accesses, against ordering only around synchronisation accesses.
More practice sits in the MCA 217 important questions.
RAW, WAR and WAW hazards in instruction pipelines: excerpt from page 53 of the MCA 217 notes
Excerpt from page 53
A hazard is any situation that stops the next instruction from executing in its planned clock cycle. The pipeline then stalls, and the empty cycle is called a bubble. Pipelines face three kinds of hazard: structural, data and control.
Structural (resource) hazards
A structural hazard appears when two instructions need the same piece of hardware in the same cycle. A common case is a single memory port that both instruction fetch (IF) and data access (MEM) want at once, or one non-pipelined divider shared by back-to-back divide instructions. The fixes are to duplicate the resource (for example, split instruction and data caches), to pipeline the functional unit, or to stall one of the two instructions.
Data hazards
Data hazards occur when data-dependent instructions sit close together. Take instruction i before instruction j, with D(i) as the set of registers i reads (its domain) and R(i) as the set it writes (its range).
- RAW (read after write): R(i) ∩ D(j) ≠ ∅, so j tries to read before i has written. Example:
ADD R1, R2, R3followed bySUB R4, R1, R5. It comes from a true (flow) dependence. - WAR (write after read): D(i) ∩ R(j) ≠ ∅, so j writes before i has read. Example:
SUB R4, R1, R5followed byADD R1, R2, R3. It comes from an anti-dependence. - WAW (write after write): R(i) ∩ R(j) ≠ ∅, so j writes before i writes. Example:
MUL R1, R2, R3followed byADD R1, R4, R5. It comes from an output dependence.
RAW is by far the most common. WAR and WAW show up only when instructions can complete out of order or when different instructions use pipelines of different lengths.
How data hazards are handled
Hardware can detect the hazard and stall (an interlock). Operand forwarding sends an ALU result straight to the next instruction's input instead of waiting for write-back. The compiler can reorder independent instructions into the gap. Register renaming removes WAR and WAW entirely, because both are name dependences rather than true data flow. The figure on this page compares a RAW stall without forwarding against the same sequence with forwarding, where the stall disappears.
Do the MCA 217 notes cover the full GGSIPU syllabus?
Yes. Every official MCA-217 topic in all four units has a matching section in the notes.
| Official unit | Official topics | Where in the notes | Status |
|---|---|---|---|
| Unit I | Evolution, Flynn's Classification, System Attributes to Performance, parallel computer models, types of parallelism, performance metrics; data and resource dependences, partitioning and scheduling; control flow, data flow and demand driven mechanisms; static and dynamic interconnection networks, bus, crossbar, multiport memory, multistage and combining networks | Sections 1-11, pages 4-24 | Covered |
| Unit II | ISA, CISC and RISC, superscalar, VLIW, SIMD design space, vector architectures, data-pipelined and systolic arrays; memory hierarchy, inclusion, coherence and locality, capacity planning, interleaving, pipelined memory access, bandwidth and fault tolerance, cache addressing models | Sections 1-10, pages 28-43 | Covered |
| Unit III | Linear and nonlinear pipelines, instruction pipeline design, hazards, scoreboarding and Tomasulo's algorithm, branch handling, static and multifunctional arithmetic pipelines, superscalar and super pipeline design | Sections 1-8, pages 47-62 | Covered |
| Unit IV | Multithreading, MIMD and multithreaded architecture, shared and distributed MIMD design, multiple-context processors; synchronisation, memory consistency, cache coherence, snoopy and directory protocols; parallel programming models, languages, compilers, environment and tools | Sections 1-8, pages 66-80 | Covered |
Official MCA 217 syllabus mapped to the notes
- Official unit
- Unit I
- Official topics
- Evolution, Flynn's Classification, System Attributes to Performance, parallel computer models, types of parallelism, performance metrics; data and resource dependences, partitioning and scheduling; control flow, data flow and demand driven mechanisms; static and dynamic interconnection networks, bus, crossbar, multiport memory, multistage and combining networks
- Where in the notes
- Sections 1-11, pages 4-24
- Status
- Covered
- Official unit
- Unit II
- Official topics
- ISA, CISC and RISC, superscalar, VLIW, SIMD design space, vector architectures, data-pipelined and systolic arrays; memory hierarchy, inclusion, coherence and locality, capacity planning, interleaving, pipelined memory access, bandwidth and fault tolerance, cache addressing models
- Where in the notes
- Sections 1-10, pages 28-43
- Status
- Covered
- Official unit
- Unit III
- Official topics
- Linear and nonlinear pipelines, instruction pipeline design, hazards, scoreboarding and Tomasulo's algorithm, branch handling, static and multifunctional arithmetic pipelines, superscalar and super pipeline design
- Where in the notes
- Sections 1-8, pages 47-62
- Status
- Covered
- Official unit
- Unit IV
- Official topics
- Multithreading, MIMD and multithreaded architecture, shared and distributed MIMD design, multiple-context processors; synchronisation, memory consistency, cache coherence, snoopy and directory protocols; parallel programming models, languages, compilers, environment and tools
- Where in the notes
- Sections 1-8, pages 66-80
- Status
- Covered
Official source: GGSIPU MCA (2 years) Scheme of Examination and Detailed Syllabus, A.S. 2025-26 onwards (MCA-217 on printed pages 117-119).
Every course in GGSIPU notes is mapped to its official PDF the same way.
Who writes and checks the MCA 217 ACA notes?
- Prateek Talwar, author: Founder, Unnati Educations; Associate Company Secretary (ACS), ICSI, membership no. 58704, since 15 May 2019; B.Com, University of Delhi (School of Open Learning), 2012. Author bio
- Ritik Rawat, subject-expert reviewer: Senior Full Stack Developer, Unnati Educations; B.Tech.
The 2026-27 edition holds 37 sections, 24 solved examples and 37 diagrams, written as Advanced Computer Architecture notes in English, with short Hinglish explainer lines. Last updated 13 October 2026, under our editorial policy.
The same team prepares GGSIPU important questions for every course.
MCA 217 and the GGSIPU MCA Sem 3 papers it connects to
The full MCA 217 entry, with unit hours and course outcomes, is in the GGSIPU MCA syllabus.
Paired lab: MCA-265 Advanced Computer Architecture Lab (1 credit) tests parallelism, memory mapping and pipelined processors from Units 1 to 3. These GGSIPU MCA Sem 3 Advanced Computer Architecture notes cover the theory paper only.
- Units 1 and 3 connect with MCA-245 Parallel Computing (Core Elective III), which repeats Flynn, Amdahl and pipeline design.
- Unit 4 coherence and consistency connect with MCA-219 Distributed Systems, the closest alternative in the same elective slot.
- Same semester core papers: MCA-201 Design and Analysis of Algorithms and MCA-203 Artificial Intelligence and Machine Learning.
How to write MCA 217 answers: formula-first numericals and twelve-mark comparison-table answers
Q1 wants crisp short answers: a definition, one formula or a three-point difference. Each 12-mark unit question usually mixes theory with a numerical or a diagram.
For numericals, write the formula, define every symbol, substitute and give units.
Slips the notes flag
- In Hwang, α in Amdahl's law is the sequential fraction.
- The pipeline clock τ is the maximum stage delay plus latch delay, not the average.
- In a collision vector, C1 is the rightmost bit.
For theory, close long answers with a comparison table: CISC and RISC, superscalar and VLIW, scoreboarding and Tomasulo, snoopy and directory protocols. Keep the precise wording: the Omega network is blocking, scoreboarding only stalls on WAR and WAW while Tomasulo removes them, and snoopy protocols do not scale.
Worked example (page 13): 80% of a program can be parallelised. Find speedup and efficiency on 8 processors.
α = 0.2, n = 8
S(8) = 1 / [α + (1 − α)/n] = 1 / (0.2 + 0.1) = 3.33
E(8) = S(8) / n = 3.33 / 8 = 0.417 (41.7%)
S(∞) = 1 / α = 5The last line earns the extra marks: a 20% serial part caps speedup at 5.
Practise this format on GGSIPU MCA important questions.
MCA 217 ACA notes FAQs
How do I get the full MCA 217 notes?
Message us on WhatsApp at 9899436384 using the Get Full Notes button on this page. The MCA 217 notes come as an 82-page printed book only and are not available as a PDF. Delivery takes 5 to 7 days at most, depending on your location. Keep the reference code in the message so the desk sends the right book.
Is MCA 217 a compulsory paper in GGSIPU MCA Semester 3?
No. MCA 217 is one of eleven Core Elective II options, and every student picks one. It carries 3 credits with 3 lecture hours a week. The scheme adds that an elective with fewer than 20 students may run without classes, and then it is completed through a MOOC with prior approval of the Programme Co-ordination Committee.
What is the passing mark for MCA 217?
MCA 217 is marked out of 100, and the end-term paper set under the official instructions carries 60 marks (12 + 48); the internal split is not printed in the syllabus PDF. The MCA scheme of examination states pass marks as 40%, which is 40 out of 100 for every paper. For end-term minimums and re-appear rules, check GGSIPU Ordinance 11 on ipu.ac.in.
Which unit of MCA 217 has the most numericals?
Units 1 and 2 each have 8 solved examples. Unit 1 works CPI and MIPS, Amdahl, Gustafson, Bernstein's conditions, hypercube and Omega routing; Unit 2 works register windows, superscalar speedup, effective access time and interleaving. Unit 3 has 5, including the reservation table to MAL problem, and Unit 4 has 3, ending with directory storage overhead.
Do the MCA 217 notes match the 2025-26 GGSIPU MCA syllabus?
Yes. They follow the MCA scheme approved by the BoS of USIC&T on 28 July 2025, which applies from academic session 2025-26 onwards. Every topic in the four official units has a matching section, shown in the syllabus map above. Because the official PDF prints no unit titles, the notes use their own titles for Units I to IV.
Is MCA 217 the same as MCA 245 Parallel Computing?
No, but they overlap. MCA 217 is a Core Elective II paper and MCA 245 is a Core Elective III paper, so you can take both. Both cover Flynn's classification, Amdahl's law, interconnection networks and pipeline design. MCA 217 goes deeper into processors, memory hierarchy and cache coherence, while MCA 245 adds PRAM and other parallel algorithms.
Get the full MCA 217 Advanced Computer Architecture Notes on WhatsApp
What is inside the MCA 217 printed notes book
- Part
- Cover and index
- Pages
- 1 to 2 (2)
- Solved numericals
- 0
- Practice questions
- 0
- Part
- Unit 1
- Pages
- 3 to 26 (24)
- Solved numericals
- 8
- Practice questions
- 20
- Part
- Unit 2
- Pages
- 27 to 45 (19)
- Solved numericals
- 8
- Practice questions
- 20
- Part
- Unit 3
- Pages
- 46 to 64 (19)
- Solved numericals
- 5
- Practice questions
- 20
- Part
- Unit 4
- Pages
- 65 to 82 (18)
- Solved numericals
- 3
- Practice questions
- 20
- Part
- Total
- Pages
- 82
- Solved numericals
- 24
- Practice questions
- 80
Format: printed book only, not available as a PDF. Delivery: within 5 to 7 days at most; the exact time may vary with your location.
Order the MCA 217 notes book on WhatsApp (4 units, 82 pages)
Unnati Educations is an independent education provider based in Vikaspuri, Delhi. We are not affiliated with, authorised by, or endorsed by Guru Gobind Singh Indraprastha University (GGSIPU). 'GGSIPU' and 'IPU' are used only to describe the syllabus our notes follow. For official information, visit ipu.ac.in.
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